The present invention relates to semiconductor packaging. In particular, the present invention relates to wafer-level semiconductor packaging.
In the fabrication of microchips, semiconductor wafers are processed and sliced into individual chips. The chips may then be used in a wide variety of devices. For example, a chip may be used in an electronic device by being electronically coupled to a printed circuit board (PCB) of the device. However, prior to such an electronic coupling packaging takes place. Packaging is the manner by which a semiconductor wafer is separated into individual chips that are then protected in various package forms. The protective packages prevent damage to the chip and provide an electrical path to the circuitry of the chip.
During packaging an underfill material, generally an epoxy adhesive, is applied between a surface of an individual chip and a substrate of the package. The underfill material secures and stabilizes the chip to the substrate. The surface of the chip includes electronic coupling mechanism, such as an array of metal bumps coupled to the internal circuitry of the chip. The coupling mechanism of the chip is configured to also electrically couple to the package through bond pads on the substrate. The underfill material is applied in liquid form and fills the space between the chip and substrate.
Dispensing of underfill material is accomplished by a heated dispensing needle. The dispensing needle is precisely positioned with respect to the chip and package. The position of the needle can greatly affect the resulting performance of the chip. For example, if underfill material contacts the opposite surface of the chip, longevity of the chip is likely affected. Additionally, if the chip is contacted by the dispensing needle, the chip will most likely be severely damaged. On the other hand, if the needle is too far from the chip, the space between the chip and the substrate may not be adequately filled with the underfill material, leading to air voids that can affect performance of the chip. In addition to dispensing needle position, the dispensing rate and viscosity of the underfill material should be accounted for to ensure uniform filling.
Generally, all of the above concerns are addressed for each and every functional chip to be packaged of the original semiconductor wafer. This can be a time consuming, expensive, and fairly inefficient process. As a result, some recent packaging developments are drawn toward wafer-level packaging. That is, rather than dispensing underfill material between each chip and each substrate, one by one, a heated liquid form of the underfill material is dispensed once, on the entire wafer. The underfill material is then cooled and solidifies and the wafer cut into individual chips. Each chip can then be individually placed on a substrate of a package. A reflow process to allow the formation of interconnects between the chip and the substrate is followed by curing of the underfill material to secure the chip to the substrate. Such wafer-level packaging can potentially save time and money.
While wafer-level packaging may be preferred from a time and efficiency standpoint, the underfill material is subject to a new set of circumstances. That is, the underfill material is no longer introduced in the confines between a chip surface and a substrate. Rather, it is delivered to an entire wafer surface, cooled, cut, and later must undergo additional curing and cooling during reflow. Unfortunately, conventional underfill material, such as the epoxy adhesive described above, has a tendency to gel and partially solidify as it is applied to the semiconductor wafer. This increases the likelihood of uneven application across the wafer surface. This can translate into uneven application to several chips simultaneously, resulting in potential adhesion and electrical coupling problems between the chip and the substrate. A single non-uniform or uneven application of underfill to a single wafer may now hamper the performance of several, if not all, chips of the wafer. Additionally, once cooled, the epoxy adhesive is particularly susceptible to damage upon sawing of the wafer, further hampering chip performance.